1. Field of the Invention
The present invention relates to a synchronous circuit of an FM multiplex broadcasting receiver for receiving two or more FM signals, each of which includes FM multiplex data.
2. Description of the Related Art
Lately, car-navigation devices which enable a driver to know the present location of his vehicle on a map while driving by detecting the location using a relative or absolute measuring method have widely spread. In such car-navigation devices, two methods of measuring the location of a vehicle are adopted. One is a method of calculating a relative location from the starting point using a gyro sensor, an azimuth sensor, vehicle speed signals or the like, and this method is called self-contained navigation. The other is a method of calculating an absolute location using a global positioning system (GPS) satellite, and is called radio navigation.
Further, it has become possible to obtain road traffic information on the car navigation devices as well as to detect the present location of user""s vehicle on the map as described above. More specifically, in Japan the Vehicle Information and Communication System (VICS) data service which is a road traffic information data service using FM multiplex broadcasting was inaugurated in 1996, whereby it is possible for the car-navigation devices to display information concerning traffic jams or other road data (suspension of traffic, road construction or the like) on the map based on the VICS data service.
In calculating an absolute location of a vehicle by a GPS satellite, there is a maximum error of 100 meters due to an intentional deterioration of accuracy which is produced to cope with a clock error of the satellite, an orbital error of the satellite, a delay error caused by an ionized layer, exploitation for criminal activities, or the like. In order to reduce such an error, a differential GPS (D-GPS) system has been developed. In this system, GPS radio waves are received by a reference broadcasting base station which has accurate data of the absolute location of a vehicle, an error between the absolute location and a location calculated based on the GPS radio waves is detected, information data of the error is transmitted to a car-navigation device using broadcasting radio waves, and then the car-navigation device obtains more accurate data concerning the location utilizing the error information data. The D-GPS (error information) data service by FM multiplex broadcasting as described above was inaugurated in 1997. With this service, it is possible to measure the location of a vehicle with a computational error of several meters.
Thus, when an FM multiplex broadcasting receiver of a car-navigation device receives VICS data or D-GPS data, a VICS data broadcasting station has to be switched to a D-GPS data broadcasting station, and vice versa.
FIG. 1 is a block diagram showing a standard FM multiplex broadcasting receiver. As the receiver shown in FIG. 1 is well known, the description thereof will be omitted. Further, FIG. 2 shows actual circuits of a block synchronous circuit and a frame synchronous circuit shown in FIG. 1.
In FIG. 2, a data counter 101 is a 2.88 centesimal counter for block synchronization. It counts a system clock of 16 kHz (a clock having the same frequency as that of a bit rate of FM multiplex data) and outputs a pulse C1 at every one block, namely, at an interval of 18 ms. Numeral 105 is a block identification code (BIC) detection circuit which detects a BIC from the data received. As will be described later, if a BIC is detected by the BIC detection circuit 105 while block synchronization is asynchronous, the data counter 101 will be reset.
Numeral 106 is a timing detection circuit which compares both the generation timing of an output pulse C1 of the data counter 101 and an output pulse BP of the BIC detection circuit 105 and detects accord or disaccord of the generation timing. When both the generation timing of the pulse C1 and the pulse BP accord, an accord pulse P1 is outputted, whereas when both the generation timing disaccord, a disaccord pulse P2 is outputted. Numeral 107 is a block synchronization determination protecting circuit. It outputs an output BL which is xe2x80x9c1xe2x80x9d representing that block synchronization has been established when the accord pulse P1 is consecutively counted prescribed M times (the number of backward protection M), and outputs an output BL which is xe2x80x9czeroxe2x80x9d representing that block synchronization has stepped out when the disaccord pulse P2 is consecutively counted prescribed N times (the number of forward protection N).
Numeral 109 is a BIC variable point detection circuit which detects a variable point of the BIC detected. For example, in FM multiplex data which constitute a frame as shown in FIG. 3, the BIC variable point detection circuit detects each variable point of BIC 1 to BIC 3, BIC 4 to BIC 2, BIC 2 to BIC 3, and BIC 4 to BIC 1. Numeral 110 is a 2.72 centesimal counter for frame synchronization and also a block counter which counts the number of blocks by counting output pulses C1 of the data counter 101. Numeral 111 is a frame synchronization detection protecting circuit. It compares a variable point detected by the BIC variable point detection circuit 109 with a variable point calculated based on a count value of the block counter 110. When the variable points accord consecutively a prescribed number of times X (the number of backward protection X), it outputs an output FL which is xe2x80x9c1xe2x80x9d representing that frame synchronization has been established. When the variable points disaccord consecutively a prescribed number of times Y (the number of forward protection Y), it outputs an output FL which is xe2x80x9c0xe2x80x9d representing that frame synchronization has been lost. When frame synchronization is asynchronous, detection of a prescribed BIC variable point causes the block counter 110 to be set to a prescribed value. Further, an output FCK from the frame synchronization detection protecting circuit 111 is a frame top signal which is generated when the block counter finishes 2.72 centesimal counting under the condition of frame synchronization.
When the FM multiplex broadcasting receiver shown in FIG. 1 attempts to obtain D-GPS data during the reception of data from a VICS data broadcasting station, the receiving frequency is temporarily switched from the VICS data broadcasting wave to a D-GPS data broadcasting wave and also block synchronization is carried out on the D-GPS data broadcasting wave, and then the receiving frequency is returned to the VICS data broadcasting wave again. Only the D-GPS data composed of two blocks are required for obtaining error information. Therefore, even though VICS data cannot be obtained during the reception of data from the D-GPS data broadcasting station, it is possible to restore the VICS data which could not be received during the reception of data from the D-GPS data broadcasting station by correcting errors in a vertical direction by vertical parity while composing a frame as shown in FIG. 3.
However, in a conventional circuit shown in FIG. 2, when the receiving wave is returned from the D-GPS data broadcasting wave to the VICS data broadcasting wave, slippage of frame synchronization of the VICS data broadcasting wave arises, whereby frame synchronization of the VICS data broadcasting wave is lost. In this situation, it is impossible not only to restore, but also demodulate the VICS data which could not be received during the reception of data from the D-GPS data broadcasting station.
Next, loss of frame synchronization of the VICS data will further be described with reference to a timing chart shown in FIG. 4. Incidentally, in this description it will be assumed that the number of backward protection M of a block synchronous circuit is two, the number of forward protection N of the block synchronous circuit is two, the number of backward protection X of a frame synchronous circuit is two, the number of forward protection Y of the frame synchronous circuit is eight, a station whose receiving frequency is F1 is a VICS data broadcasting station, and a station whose receiving frequency is F2 is a D-GPS data broadcasting station.
In receiving data from the D-GPS data broadcasting station, consecutively received data equivalent to two blocks can secure a practically sufficient error rate merely by a horizontal error correction of the blocks, thereby enabling demodulation and reproduction of the D-GPS data. Therefore, assuming that D-GPS data are received from the D-GPS data broadcasting station during the periods of T12 and T13 shown in FIG. 4, a receiving frequency of the D-GPS data broadcasting station will be switched during the periods of T7 through T14 (receiving frequency). Further, timing of data transmission from the VICS data broadcasting station is illustrated on the basis of a BIC in the data (transmission data F1). Similarly, timing of data transmission from the D-GPS data broadcasting station is illustrated on the basis of a BIC in the data (transmission data F2). As described above, data equivalent to eight blocks transmitted from the D-GPS data broadcasting station are inputted to the block synchronous circuit and the frame synchronous circuit shown in FIG. 2 during the periods of T7 through T14. On the other hand, during the other periods, data of the VICS data broadcasting station are inputted to the block synchronous circuit and the frame synchronous circuit. Further, timing of detecting a BIC by the BIC detection circuit 105 is timing of data (F1) transmission in the case of the reception of data from the VICS data broadcasting station and is timing of data (F2) transmission in the case of the reception of data from the D-GPS data broadcasting station (receiving data).
In the block synchronization determination protecting circuit 107, the number of forward protection N is set to two and the number of backward protection M is set to two, respectively. Thus, when the receiving frequency is switched from the VICS data broadcasting station to the D-GPS data broadcasting station, block synchronization of the VICS data broadcasting station is lost at the period of T9 and block synchronization of the D-GPS data broadcasting station is established at the next period of T10. Therefore, an output BL becomes 0 at the period of T9 and 1 at the period of T10. As the receiving frequency is returned from the D-GPS data broadcasting station to the VICS data broadcasting station at the period of T15, block synchronization of the D-GPS data broadcasting station is lost at the period of T16 and block synchronization of the VICS data broadcasting station is established at the period of T18. Meantime, the output BL becomes 0 at the period of T16 and 1 at the period of T18.
If the data counter 101 has been reset prior to the period of T0 at the data transmission timing of the VICS data broadcasting station, the data counter 101 will operate in such a manner that it synchronizes with the data transmission timing of the VICS data broadcasting station until the period of T8 and it is reset after counting 288. Since the data counter 101 will be reset by a pulse BP if an output BL is 0, block synchronization of the VICS data broadcasting station will be lost at the periods of T9 and T10 and an output BL becomes 0. A reset signal will then be generated in response to a BIC of the D-GPS data broadcasting station which is received at the period of T9. Thus, the data counter 101 will be reset before counting 288, whereby an output C1 will not be outputted. Similarly, block synchronization of the D-GPS data broadcasting station is lost and an output BL becomes 0 at the periods of T16 and T17. Thus, a reset signal is generated in response to a BIC of the VICS data broadcasting station which is received at the period of T17 and the data counter 101 is reset before counting 288, whereby an output C1 is not outputted. Incidentally, saw tooth waveform of an output of the data counter 101 shown in FIG. 4 indicates a change of counted value of the data counter 101. More specifically, it shows that the value will return to 0 after completion of 288 counts in the case of synchronization with the data transmission timing, but the value will return to 0 before the completion of 288 counts if a reset signal is generated.
Thus, since generation of an output C1 of the data counter 101 does not synchronize with the data transmission timing at every change of the receiving frequency (C1), a shortage of count arises at the block counter 110 (block counter) and a frame top signal (FCK) deviates from the frame top of a signal actually transmitted (a vertical dotted line in FIG. 4) (frame top). As a result, a block count for frame synchronization deviates and frame synchronization is lost.
The purpose of the present invention is to provide a synchronous circuit of an FM multiplex broadcasting receiver which can prevent loss of synchronization when receiving FM signals from a plurality of FM multiplex broadcasting stations.
According to the present invention, due to a counter which carries out a counting operation at timing of receiving multiplex data from each broadcasting station, it is possible to maintain block synchronization of not only a station from which the data are being received, but also a station from which no data are currently being received. In particular, when a single broadcasting radio receiver is used to receive multiplex data from two stations having different data transmission timing by switching the receiving frequencies, even though the receiving frequency is switched from one broadcasting station to the other broadcasting station only for a certain period, it is possible to accurately maintain frame synchronization of multiplex data of the former.
For example, a first counter and a second counter perform a counting operation at two different timings of receiving multiplex data and the respective counters maintain the counting operation. In response to a synchronization control signal, an output of the first counter is selected during a period of receiving multiplex data at one timing and an output of the second counter is selected during a period of receiving multiplex data at the other timing. Based on the output, block synchronization is detected. Further, detection of frame synchronization when receiving multiplex data at one timing is always performed based on an output of the first counter. Thus, it is possible to prevent loss of frame synchronization which may occur resulting from miscounting of block synchronization at every change of the broadcasting station.
Further, according to another aspect of the present invention, the first and second counters perform a counting operation at two different timings of receiving multiplex data, and when FM signals are switched, a synchronous condition of a block synchronous circuit is forcibly reset and the counting operation is synchronized with the timing of receiving FM multiplex data which are represented by FM signals switched to one counter. Thus, without impeding counting operation of the other counter, the counting operation of one counter can be synchronized with timing of receiving the FM multiplex data. Since detection of frame synchronization when receiving FM multiplex data at the other timing is always performed based on an output of the other counter, it is possible to prevent a step-out of frame synchronization which may occur resulting from miscounting of block synchronization at every change of the broadcasting station.
Further, it is possible to maintain frame synchronization more reliably by suspending the detection of frame synchronization while receiving data from the other broadcasting station.